An asynchronous low power RSA circuit structure and its modular multiplication circuit structure for smart cards and RFID tags are proposed. By using GTECH optimization scheme and BrzCallMux implementation strategy, ASIC implementation is carried out based on a TSMC 130 nm standard CMOS technology. Experimental results show that the area of the proposed asynchronous low power RSA is only 4% of that of another asynchronous RSA, its average time to perform a cryptographic operation is only 0.216% of that of another asynchronous RSA, and its power consumption is only 16.99% of that of its corresponding synchronous counterpart.

A non-invasive, high-efficient and low-cost fault attack is realized on FPGA-based cryptographic applications. Based on the setup failures in critical paths, faults are injected into the FPGA devices by lowering the supply voltage. Then the encryption key can be retrieved efficiently with an appropriate fault model. In the attack experiments, the full 128-bit key of AES is retrieved correctly with only 8 pairs of correct and faulty ciphertexts within a few minutes, by using a power supply and a personal computer, based on the FPGA platform.

The authors present a drive and sense interface for MEMS vibratory gyroscopes. A gm-stage and a TIA are employed as the first stage to achieve low-noise C/V conversion. The signals of both drive mode and sense mode are converted to digital domain by integrated 1.25 MS/s 14-bit SAR-ADCs. With this strategy, the complexity of the analog circuit is reduced, and the signal in digital domain can be manipulated more accurately. The interface is applicable for the MEMS gyroscopes whose resonant frequency is from 3 kHz to 15 kHz. The circuit is designed in a 0.18μm CMOS process. Experimental results show that the capacitive noise density of the output is achieved to 0.03 aF/√Hz at 3.5 kHz.

The authors propose a novel countermeasure which associates masking with RDI (random delay in- sertion). Further, multi-masking instead of transformed masking is proposed in order to defend DPA (differential power analysis) attack based on Hamming distance model. The combined countermeasure is implemented on Data Encryption Standard. The results show that combined countermeasure can defend DPA attack with 10⁵ power traces, and increase 40% ability against DPA attack.

Radio frequency identification (RFID) suffers extremely limited chip area and energy resource. A novel elliptic curve cryptographic (ECC) processer based on generalized binary Hessian curve (GBHC) is designed and implemented. The authors employ Montgomery Ladder scalar-multiplication algorithm and optimized w-coordinate method for accelerating the computing timing, and well-design circular shift register (CSR) architecture and clock gating technology for reducing the consumption of area and energy. The results show that the proposed processer has fast computing speed, minimal chip area and ultra-low energy consumption, and is capable to resist some types of side channel attack (SCA) such as simple power analysis (SPA).

The authors studied the DPA attack method and circuit level protection technology, and introduced a security circuit WDDL on FPGA and a new symmetrical routing technology. A 4-bit WDDL adder on FPGA (field programmable gate array) platform was implemented and the power consumption of the circuit was analyzed. The results show that power consumption of WDDL decreases obviously than that of the traditional circuit and WDDL circuit can reduce the correlation of power consumption and data effectively. WDDL is proved to have better anti DPA (differential power analysis) attack ability at the cost of chip size.

To study the vulnerability of Advanced Encryption Standard (AES) against electromagnetic side channel attacks, based on the method of correlation electromagnetic analysis (CEMA) attack, the authors built a platform to acquire EM emanation and process data, then performed a near-field CEMA attack against an FPGA implementation of AES-128. The results indicate that the platform is able to acquire the EM emanation of the encryption chip, and can retrieve all the 16 bytes of the 10th roundkey of AES. After the optimization of processing data, the efficiency of CEMA is highly enhanced, namely the data needed to exploit the correct roundkey is greatly reduced.

The authors discuss the performance and area of different large-scale Booth multipliers with high radices used in Montgomery algorithm using secondary encoded scheme. The modular multiplication is implemented with SMIC 0.13μm technology at the frequency of 160 MHz and 125 MHz respectively based on the 128-bit multiplier and 256-bit multiplier with Booth 64, 128 and 256 encoding. Experiment result shows that the multiplier with Booth 64, 128 and 256 can achieve the same timing performance, while the area rises as radix rises due to the complexity in pre-computation and partial product generation.

A dynamic reconfigurable digital system is proposed. By defining modulation and demodulation as reconfigurable modules, the proposed modem changes its modulation scheme and data rate according to underwater channel estimation results to provide low bit error rate and low energy consumption communication. The digital system is implemented on Xilinx XUPV5 FPGA board. Hardware and software co-verification show that the digital system works correctly and can be reconfigured to 2FSK and 2PSK mode. Compared to traditional FPGA development approach, dynamic reconfigurable design method improves flexibility of algorithm design and saves resource utilization of the digital system.

This paper presents the design, optimization and implementation of GPS carrier tracking loop based on high sensitivity GPS base band signal processor research topic. The phase detector, loop error sources and loop parameters are first optimized to improve the tracking sensitivity and then the phase lock loop assisted by frequency lock loop circuit structure is applied. The circuit is optimized and timing-sharing technology is used for the modules including several multipliers and dividers to reduce resource consumption and save chip area. The authors implement the designed GPS carrier tracking loop in Verilog and complete the logic and functional simulation in Modelsim with RTL level code. The FPGA board verification platform is established and the performance test is carried out using GPS L1 band signal source. The test result shows that the tracking sensitivity can reach 25 dB-Hz and chip area of the single channel carrier tracking loop is 425555μm² in SMIC 0.18μm technology using Design Complier.

The authors present a control scheme for UWModem with embedded processor in FPGA. The scheme builds system structure by choosing suitable communication bus type, and designs rational soft/ hardware cooperating procedure and interrupt controlling signals. The results from soft/hardware co-verification with MicroBlaze soft processor in Xilinx VirtexIV FPGA show that the control scheme can efficiently manager the whole digital signal processing in UWModem and report the situation in real-time with steady performance.

The authors propose an optimizing method for the energy detector based on the parallel correlators in the time domain. With a method named as two-step correlation method and time sharing techniques, all the 1023 chip phases are detected in parallel. When the sampling frequency is 16. 368 MHz, the total correlator number is reduced to be 1/ 102. 3 of the non-optimized counterpart. Furthermore, the energy detector using the proposed method is implemented by FPGA and synthesized with Design Compiler. The test results show that when pre-detection time is 2s, C/N₀ = 21 dB-Hz, and false alarm is 0. 097% , the detection probability is as high as 90% .

A high speed VLSI decoder architecture is proposed for a standard forward error correction(FEC) in optical network. In the proposed parallel decoder architecture, a novel parallel computation of syndrome is presented to reduce the hardware complexity. A method is introduced to derive an inversion-free algorithm from the decision tree algorithm with the number of correctable errors less than 5. Area and timing estimates obtained by logic synthesis with 0.18 CMOS technology show that the implementation of (4359,4320)BCH (Bose-Chaud huri-Hocquenheim) decoder can achieve 248 MB/s with an estimated area of 0.31 mm² including the embedded memory to store the received words. Compared with serial decoder, the proposed parallel architecture can achieve 8 times throughput with less than 2 times area.

The authors analyze the detailed process of calculator schedule in high speed FIR (finite impose response) digital filter with add-and-shift algorithm based on FPGA (field programmable gate array). Different calculation situations and related schedule schemes are discussed and a clear rule of optimization is proposed. At last, an example of a 16-order FIR filter is implemented on Xilinx Spartan 3 3s1000ft256 FPGA platform. The occupied resource is 11.7% less than the one generated without optimization and/or 29.7% less than the one generated by Xinlinx Coregen^TM with distribute arithmetic (DA), respectively.

A behavioral simulation method is proposed for both system level and behavioral level design of Sigma-Delta ADCs (analog to digital converters).Compared with traditional behavioral simulation methods，the proposed method has a higher simulating speed and is more efficient in the behavioral design.With this simulation method，the imperfections of the analog cells as integrators，comparator，and the Op-Amps are analyzed in detail，which guides the design towards high performance. As a proof for the effectiveness of this method，a second-order Sigma-Delta modulator was designed and fabricated using a 0.13 μm mixed signal CMOS technology.The test results show that the modulator can achieve a peak SNR of 77.2 dB，which equals to a 12.5 bit resolution，and a power dissipation of 5.9 mW (6.2 mW with decimator) was occupied.

52-level scalar quantization technology plays an important role in H.264/AVC. A novel parallel VLSI architecture is proposed for its hardware implementation, in which the 4×4 matrix multiplications is replaced by 16 unsigned compressed shift-adder-trees using partial CSD code scheme, switching reference wirings substitutes for look-up operation, and division is also avoided effectively, and no ROM or RAM is adopted in the overall quantizer. It can fulfill all the quantization calculations for all H.264 hybrid transform in 4×4 block parallelism. Its block throughput can reach 121.6MHz, which can meet the real-time requirement for 4096×2304@120Hz (119.43936M/s) video compression. Compared with the conventional architecture, 38% cost and 30% power are saved. Considering speed and cost optimization, this architecture is very suitable for pipeline acceleration, and it is a useful IP for high resolution H.264 encoder VLSI realization.

A low power FFT (Fast Fourier Transform) processor based on Single-path Delay Feedback (SDF) architecture is proposed. Power optimization strategy based on statistical characteristics of input data is applied in the design. Both the advantages and the drawbacks of this strategy are analyzed in detail, and solutions to overcome the drawbacks are addressed. An experimental 64-point FFT processor model is implemented in SMIC 0.18 μm CMOS technology, and for given input signals, 15% power reduction can be achieved.

An efficient low complexity H.264 VBSME (variable-block-size motion estimation) VLSI (very large scale integrated) architecture is designed, in which a MB-size input buffer, 17×16 snake scan register array, 8×8 PE array,4×4 SAD-adder-tree are used and a four-step VBS MV generator structure is proposed to reduce the hardware cost for wireless video communication applications. Compared with the MB-level VBSME structure, the total count of gates is reduced to 37%, the delay of critical path is shorten from 9.8 ns to 8.2 ns, and nearly 50.3% power is saved and the main data-path width is narrowed to 25%, but all MB characters are reserved. Its low-hardware-complexity performance makes it suitable for the integration of H.264 encoder in wireless video communication applications.

The authors describes an efficient design and implementation of a decimation filter for high resolution 2nd ΣΔ A/D converter. A new universal multiplier, free VLSI structure is proposed to implement 2, time decimation for half band filters and a high, order invsinc corrector filter, the whole filter is realized without any multiplier or RAM or ROM, and the 2nd ΣΔ A/D converter reaches a 16, bit resolution with low cost.

Based on the classical system design flow, a custom digital down converter (DDC) was designed and implemented for Homenet wireless communication system. At the system level, the behavior model of DDC was constructed with the assistant of system modeling tool MATLAB. At the circuit level, considering implementation complexity, a large number of digital filter optimizing schemes such as CSD and RAG were adopted; in our design, numerically controlled oscillators (NCO) was based on a new hybrid scheme, which combines the respective advantages of LUT and CORDIC algorithm. Homenet system verification flat including our custom digital down converter was implemented with Xilinx VirtexII XC2V1000-4FG256 FPGA.

A new latched comparator architecture was proposed. Because of its very low kickback noise feature, it is especially suitable for differential analog-to-digital converters (ADCs). Simulated results of the proposed circuit in a 0.35μm standard CMOS technology show that this comparator achieves a sampling speed of 400 Ms/s at 3.3V supply, with a kickback noise 88% lower than conventional schemes.

Modular exponentiation of large operands is the kernel operation in many public-key cryptosystems, RSA algorithm for instance. Montgomery algorithm is often used as a solution. In the VLSI implementation of Montgomery algorithm, the speed is the top target. An improvement is proposed with little or even no increase in the hardware area but apparently saving much time.